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Home - Reader Forum: Targeting RAN power needs
Chips - SemiconductorNetwork InfrastructureReader Forum

Reader Forum: Targeting RAN power needs

by jscarbo July 26, 2010
written by jscarbo July 26, 2010 Share
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Editor’s Note: Welcome to our weekly Reader Forum section. In an attempt to broaden our interaction with our readers we have created this forum for those with something meaningful to say to the wireless industry. We want to keep this as open as possible, but maintain some editorial control so as to keep it free of commercials or attacks. Please send along submissions for this section to our editors at: [email protected]@ardenmediaco.com.
Over the next five years, it is universally agreed, LTE and other 4G technologies will blanket the wireless landscape and deliver the greatest possible bandwidth over available spectrum. It is further agreed that delivering this bandwidth across each operator’s network, to achieve consistent broadband user satisfaction, will be a serious challenge stressing both capital expenditures and operating expenditure budgets.
What is not agreed is how radio access nodes will be deployed to meet that challenge, how much capex will be required, and how serious the impact on opex will be. HetNet architectures including micro- or pico-cells, and active antennas, are viewed as key to an economic solution but confront an acute issue – the need for a much larger number of smaller, lower power, low cost, and highly efficient radio transmitters. What innovations are required to enable this transition in an economically viable manner? Is there a cost-effective solution on the horizon?
Pervasive use of programmable digital signal processing, in the baseband sections of radio access nodes, has been key to enabling today’s 3G wireless networks. In the past, however, it was not possible to use these approaches in the carrier-frequency RF sections, and these modules are designed today much as they were 30, 40 and 50 years ago. A great example is the Doherty power amplifier, which was patented in 1934 – albeit with vacuum tubes – and deployed with transistors as “state of the art” into the cellular infrastructure over the last decade.
While no one expects that it will be practical to extend DSP to multi-GHz signals in the next five to 10 years (due to clock speed, power, and ADC constraints) a favorable alternative is emerging. A CMOS-based signal processing chip, recently introduced and beginning to appear in infrastructure products, performs a range of traditional DSP functions at radio frequencies up to 3.5 GHz – while requiring less than 10% of the power of even lower frequency DSP solutions. The key innovation is to partition the problem and, while keeping many slower speed functions in the digital domain, to perform all of the carrier frequency functions in the analog continuous time domain – requiring no A/D or D/A conversion in the RF signal path.
The first application released on this novel platform is an adaptive pre-distorter for power amplifier linearization. System design is greatly simplified by moving the function from baseband to the carrier frequency, cost is significantly lower than for baseband digital pre-distortion solutions, and power requirements are slashed. Implementation of the pre-distortion function with this platform solves one of the fundamental problems in the realization of the compact, low cost, and low power radios needed for 4G HetNets – highly efficient radios that will break neither opex nor capex budgets can now be successfully realized.

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